Field of the Invention
This field of the present application relates in general to a method for the fabrication of layered planar elements and a fabrication unit for layered substantially planar elements and to a method for the processing of semiconductor wafers (including photovoltaic devices) and a fabrication unit for semiconductor wafers. The field of the application also relates to a method of calculating process correction parameters in the field of processing of semiconductor wafers.
Brief Description of the Related Art
It will be appreciated that the term “semiconductor wafer” as used in this disclosure is intended to imply wafers used in the manufacture of all types of semiconductor devices, including, but not limited to, microelectronic circuits, such as memory devices and ASICS, liquid crystal panels, and photovoltaic devices.
Current trends in the processing of the semiconductor wafers means that overlay budgets shrink with shrinking ground rules, and manufacturing processes are becoming more aggressive. Non-limiting examples of such aggressive manufacturing processes include high aspect ratio etching or deposition of exotic materials on a surface of the semiconductor wafer. The non-uniformity of some manufacturing processes over the semiconductor wafer surface and a plurality of manufacturing process steps may result in non-uniform stress being applied to the semiconductor wafer. When the semiconductor wafer deforms from one manufacturing process step to a subsequent manufacturing process step, e.g. from one lower layer to a subsequent layer on top of the lower layer, patterns in the upper layer become misaligned to patterns in the lower layer. For the error free functioning of a semiconductor the relative position of patterns on the different layers to each is relevant. These relative positional errors are termed “overlay errors”. The need for smaller and denser structures on the semiconductor wafer means that an allowable tolerance for the overlay errors decreases.
The overlay error is determined by means of so-called “overlay marks”. In a lower layer together with the pattern for the semiconductor structure of the process step a first set of overlay marks are exposed in a photoresist film. After developing and processing this lower layer, the first overlay mark becomes part of the structure of this lower layer. On a higher layer in a subsequent process step together with the pattern for the semiconductor structure of the higher layer, a second set of overlay marks is exposed in a photoresist film. After development of the photoresist film the relative position error between the first overlay mark on the lower layer and the second overlay mark on the top layer can be measured in an overlay measurement tool. If the tolerance of the overlay error is too large the semiconductor wafer may be reworked with applied corrections. The goal is to use the measured overlay errors to compensate for the overlay errors in a next lot of semiconductor wafers, so as to minimize the overlay errors in the next lot and thus avoid costly rework.
The concepts of alignment and overlay are different. The alignment of a semiconductor wafer is performed within an exposure tool to align semiconductor wafers prior to exposure. Typically one alignment mark is used per exposure field. The measurement of the overlay error is performed after the exposure and development of the photoresist film when the second set of overlay marks have been formed in the layer defined by the photoresist film. There are typically several overlay marks for each exposure field.
A number of prior art documents are known for using alignment marks on the semiconductor wafer to improve overlay control. For example, US 2010/0030360 teaches a method of calculating “alignment residuals” in a fabrication unit is known that comprises providing an alignment model including alignment model parameters; providing an exposure tool suitable for exposing a lot of semiconductor wafers in a plurality of exposure fields; retrieving alignment data comprising alignment values, measured by the exposure tool on the semiconductor wafers of the lot at a plurality of positions of the exposure fields that are used to calculate values for the alignment model parameters of the alignment model; calculating a set of alignment residuals from the alignment data by subtracting effects of the alignment model parameters for each of the plurality of measured positions and for each of the semiconductor wafer in the lot; and issuing a warning signal based upon a comparison between the set of alignment residuals and a set of reference values. The U.S. '360 document further comprises a system for calculating alignment residuals and a computer readable medium including instructions capable of performing the steps of calculating alignment residuals on a computer.
Chun-Yen Huang et al “Overlay improvement by zone alignment strategy”, Proceedings of SPIE, Vol. 6922, 1 Jan. 2008, pages 69221G-1-69221G-8 teaches the so-called zone alignment strategy in which the alignment marks on the wafer are measured zone by zone in order to provide additional correction factors (residuals) for the zones on the wafer (see page 69221G-3). The method taught in Huang et al. weights the values of residuals for the neighbouring alignment marks.
Michael Kupers et al “Non-linear methods for overlay control”, Proceedings of SPIE Vol. 6518, 1 Jan. 2007, pages 65184S-1-65184S-6 also teaches a method for improving overlay control by a zone-alignment strategy.
U.S. Pat. No. 5,525,808 (Irie et al, assigned to Nikon) teaches also the zone alignment strategy for the improvement of overlay. The U.S. '808 Patent teaches a method of aligning each of a plurality of processing areas regularly aligned on substrates according to designed alignment coordinates to a predetermined reference position in a static coordinate system. The method comprises measuring coordinate positions of at least three processing areas of the wafer selected in advance. The method further comprises determining coordinate positions of the plurality of processing areas on the semiconductor substrate by weighting the coordinate positions of the three specific processing areas according to distances between the processing area of interest and each of the three specific processing areas in units of processing areas on the substrate. Finally, a statistical calculation is performed using the plurality of the weighted coordinate positions. The teachings of the U.S. '808 patent relate once again to the alignment of the semiconductor wafer (substrate) and not to correction of overlay errors by measuring overlay deviations and calculating process correction parameters.
None of the cited documents teach the measurement of overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences of subset of first overlay marks generated in the first layer and corresponding one of the subset of second overlay marks generating the second layer. The zone alignment strategy disclosed in the art uses alignment marks, which are used to align the wafer within the exposure tool. These alignment marks are different than the overlay marks formed in different layers on the semiconductor wafer.
Ideally overlay measurements should be taken for each one of the semiconductor wafers after exposure of the photoresist layer at multiple positions on each exposure field on each of the semiconductor wafers to achieve a degree of precision and thus to achieve high yield rates for the fabrication of the semiconductor wafers. However, complete overlay measurements are very slow to perform, so they may cause a tool capacity problem. In other words, the time taken to perform a complete overlay measurement is a multiple of the time taken to process the semiconductor wafer. Thus, in order to provide the overlay measurements of each of the semiconductor wafers, a number of overlay measurement units has to be provided to distribute the overlay measurements on several parallel organised overlay measurement units.
The overlay measurement units are a significant cost factor in a semiconductor manufacturing process and for cost reasons the deployment of the parallel organised overlay measurements units is avoided. Another solution for reducing limitations in the semiconductor manufacturing process whilst not extending the number of the overlay measurement units is to measure the overlay measurements in only a subset of the semiconductor wafers.